Inductor for semiconductor integrated circuit and method of fabricating the same

ABSTRACT

Disclosed are an inductor for a semiconductor integrated circuit, which provides a wider cross-sectional area, significantly reduces the resistance to improve the Q value and has a highly uniform film thickness, and a method of fabricating the inductor. A spiral inductor is formed on a topmost interconnection layer of a multilayer interconnection layer formed by a damascene method. This inductor is formed by patterning a barrier metal layer on an insulation film, on which a topmost interconnection is formed, in such a way that the barrier metal layer contacts the topmost interconnection, then forming a protective insulation film on an entire surface of the barrier metal layer, forming an opening in that portion of the protective insulation film which lies over the barrier metal layer, forming a thick Cu film with the barrier metal layer serving as a plating electrode, and performing wet etching of the Cu film. This process can allow the inductor to be so formed as to be thick and have a wide line width.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an inductor which is formed in asemiconductor integrated circuit and a method of fabricating theinductor.

2. Description of the Related Art

A conventional inductor provided in a semiconductor integrated circuitis formed on the same layer as the interconnection of the topmost layerof a multilayer interconnection formed by a damascene process (seeJapanese Patent Laid-Open No. 2001-267320). FIG. 1 is a cross-sectionalview of a semiconductor integrated circuit including a conventionalinductor. Wells 2 and 3 are formed in the surface of a substrate 1, anda pair of high-concentration diffusion layers 6 of an MOS transistor anda low-concentration diffusion layer 7 lying between the diffusion layers6 are formed in an area which is defined by device isolation regions 4and 5 on the surface of the well 2. A gate insulation film 8 is formedon the substrate between the diffusion layers 6, and a gate electrode 9and a side-wall insulation film 10 on the sides of the gate electrode 9are formed on the gate insulation film 8. This provides an MOStransistor with an LDD (Lightly Doped Drain) structure.

A multilayer interconnection is formed on the substrate 1. Specifically,a first interlayer insulation film 11 is formed on the substrate 1, anda first interconnection layer 12 is formed on the first interlayerinsulation film 11. The first interconnection layer 12 is formed by thefollowing process. First, as shown in FIG. 2A, after a contact hole 21is formed in the first interlayer insulation film 11, an insulation film11 a is formed on the first interlayer insulation film 11. Then, asshown in FIG. 2B, a groove 22 a for an interconnection 22 is formed inthe insulation film 11 a by forming a resist pattern on the insulationfilm 1 a by photolithography and then dry-etching the insulation film 11a with the resist pattern as a mask.

Next, as shown in FIG. 2C, a thin metal film 32 (TaN film or the like)to be a plating electrode is formed on the surface of the bottom andsides of the groove 22 a for the interconnection 22 by sputtering or thelike, and a barrier metal layer 23 is formed on the bottom of the groove22 a after which Cu is buried in the groove 22 a for the interconnection22 by plating Cu with the metal film 32 as a cathode. In this case, Cuis also deposited on the insulation film 11 a.

Thereafter, as shown in FIG. 2D, Cu on the insulation film 11 a isremoved by CMP (Chemical Mechanical Polishing) to expose the insulationfilm 11 a and planarize the surface of the insulation film 11 a and thesurface of the of Cu buried in the interconnection groove 22 a. As aresult, a buried interconnection 22 is formed in the firstinterconnection layer 12.

Using the damascene method, likewise, a second interlayer insulationfilm 13 is formed on the insulation film 11 a, a contact hole 24 isformed in the second interlayer insulation film 13, and aninterconnection 25 of a second interconnection layer 14 is formed on aninsulation film 13 a formed on the second interlayer insulation film 13.Further, a third interlayer insulation film 15 is formed on theinsulation film 13 a, a contact hole 26 is formed in the thirdinterlayer insulation film 15 and an interconnection 27 of a thirdinterconnection layer 16 is formed on an insulation film 15 a formed onthe third interlayer insulation film 15. Furthermore, a fourthinterlayer insulation film 17 is formed on the insulation film 15 a, acontact hole 28 is formed in the fourth interlayer insulation film 17and a topmost interconnection 29 of a topmost interconnection layer 18is formed on an insulation film 17 a formed on the fourth interlayerinsulation film 17. The barrier metal layer 23 is also formed on thebottom of the topmost interconnection 29 and another barrier metal layer31 is formed on the top of the topmost interconnection 29. A protectivefilm 19 is formed on the entire surface of the resultant structure.

In a semiconductor integrated circuit which has the conventionalinductor, therefore, the coil-like inductor 30 is formed simultaneouslyat the time of forming the topmost interconnection 29 of the topmostinterconnection layer 18. That is, at the time of patterning the groovefor the topmost interconnection 29 of the topmost interconnection layer18 in the insulation film 17 a by photolithography, the groove for theinductor 30 which is a coil-like interconnection is patternedsimultaneously. Then, after a thin film for the plating electrode isformed by sputtering, the Cu film is formed by electrolytic plating insuch a way as to be buried in that groove, then the surface is subjectedto CMP to planarize the surface.

In the conventional semiconductor integrated circuit, the inductor 30 isformed together with the topmost interconnection 29 on the topmostinterconnection layer 18 of the multilayer interconnection layer, formedby the damascene method, in the above-described manner.

Because the inductor 30 is formed at the same time as the topmostinterconnection 29 by the damascene method in the conventionalsemiconductor integrated circuit, however, the thickness of the inductor30 is limited by the thickness of the topmost interconnection layer 18.There is a limit to the thickness of the topmost interconnection layer18 due to the restrictions on the fabrication process. As shown in FIG.2D, “dishing”, a phenomenon which produces a recess portion as thecenter of the surface of the interconnection is etched, occurs in theabove-described CMP process in the damascene method. The wider theinterconnection is, the more noticeable this “dishing” becomes. Thisputs some restriction on the width of the interconnection of theinductor 30.

Because of the restrictions on the interconnection width and the filmthickness, the conventional inductor cannot have a large cross-sectionalarea. The conventional inductor disadvantageously has a high resistancewhich makes it difficult to improve the Q value that indicates theperformance of the inductor.

Further, the surface, 33, of the interconnection 22 undergone CMP isrecessed by dishing as shown in FIG. 2D, resulting in poor filmplanarization. Due to a variation in conditions for CMP, the uniformessof the film thickness of the inductor is poor, which is likely to causea variation in the characteristics.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the invention to provide an inductor fora semiconductor integrated circuit, which provides a widercross-sectional area, significantly reduces the resistance to improvethe Q value and has a highly uniform film thickness, and a method offabricating the inductor.

An inductor for a semiconductor integrated circuit according to theinvention comprises a substrate; an interconnection layer formed on thesubstrate by a damascene method; and an inductor formed by patterning aconductive layer laid on the interconnection layer.

In the inductor, for example, the conductive layer is, a copper layer ora copper alloy layer and the inductor is patterned by anisotropicetching of the conductive layer.

The anisotropic etching is, for example, wet etching. For example, theconductive layer is formed by plating. The inductor may further comprisea bonding pad formed outside the inductor by patterning the conductivelayer.

Another inductor for a semiconductor integrated circuit according to theinvention comprises a substrate; a plurality of interconnection layersprovided on the substrate; a plurality of interlayer insulation filmslaid between the interconnection layers and between a topmost one of theinterconnection layers and the substrate; and an inductor formed on thetopmost interconnection layer. Each of the interconnection layers has afor-interconnection-layer insulation film and an interconnection formedby forming a groove in the for-interconnection-layer insulation film,then burying a conductive material in the groove and planarizing asurface of the for-interconnection-layer insulation film by chemicalmechanical polishing. The inductor is formed by forming a conductivelayer on the topmost interconnection layer via an insulation film andthen patterning the conductive layer.

In the inductor, for example, the conductive layer is formed by platingand the conductive layer is a copper layer or a copper alloy layer.

The inductor is patterned by, for example, anisotropic etching and theanisotropic etching is, for example, wet etching.

The inductor may further comprise a bonding pad formed by patterning theconductive layer and is formed at the same time as the bonding pad.

The inductor may be connected to the topmost interconnection layerunderlying the insulation film via an opening provided in the insulationfilm. The inductor may be constructed in such a way that theinterconnection of the topmost interconnection layer is in contact withthe inductor in a lengthwise direction thereof and the interconnectionof the topmost interconnection layer functions, together with theinductor, as an inductance.

A method of fabricating an inductor for a semiconductor integratedcircuit according to the invention comprises the steps of forming, on asubstrate, a multilayer interconnection layer by a damascene method,which is formed by alternate lamination of interlayer insulation filmseach having a contact hole formed therein and interconnection layerseach formed by burying a conductor in a for-interconnection-layerinsulation film; forming a conductive layer on the multilayerinterconnection layer; and forming an inductor by patterning theconductive layer in a spiral form by anisotropic etching.

In the method, the step of forming the conductive layer is, for example,a step of depositing a conductive layer by plating. The anisotropicetching may be wet etching.

In the step of forming the inductor, a bonding pad may be formed fromthe conductive layer at a same time.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view showing a conventional inductor for asemiconductor integrated circuit; and

FIGS. 2A through 2D are cross-sectional views showing the process offorming the interconnections of the inductor (including the inductor)step by step;

FIG. 3 is a cross-sectional view showing an inductor for a semiconductorintegrated circuit according to a first embodiment of the invention;

FIG. 4 is an exemplary perspective view showing the inductor portion;

FIGS. 5A through 5D are cross-sectional views showing the fabricationprocess for the inductor step by step;

FIG. 6 is an exemplary perspective view showing the inductor portion ofan inductor for a semiconductor integrated circuit according to a secondembodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of the invention will be described below withreference to the accompanying drawings. FIG. 3 is a cross-sectional viewillustrating an inductor according to the first embodiment of theinvention, FIG. 4 is a perspective view showing the inductor portion inenlargement, and FIGS. 5A through 5D are cross-sectional views showingthe fabrication process for the inductor step by step. To avoid theredundant description, like or same reference symbols are given to thosestructural elements in FIG. 3 which are the same as the correspondingelements shown in FIG. 1.

In FIG. 3, a multilayer interconnection is formed on a substrate 1 bythe damascene method and the inductor in FIG. 3 is the same as theconventional inductor for a semiconductor integrated circuit shown inFIG. 1 up to a point where a contact hole 28 is formed in the fourthinterlayer insulation film 17 which is the topmost layer as aninterlayer insulation film. An insulation film 17 a is formed on thefourth interlayer insulation film 17, a groove for a topmostinterconnection 29 is patterned on the z17 a by the damascene method,then the groove is plated and buried with Cu after which the surface ofthe resultant structure is planarized by CMP, thereby forming theinterconnection 29. In the embodiment, the inductor is not formed onthis topmost interconnection layer 18.

A spiral inductor 40 according to the embodiment is formed on thetopmost interconnection layer 18. A method of forming the inductor 40will be discussed next. First, as shown in FIG. 5A, a barrier metallayer 41 is patterned on the insulation film 17 a, on which the topmostinterconnection 29 is formed, in such a way as to contact the topmostinterconnection 29, after which a protective insulation film 42 isformed on the entire surface of the resultant structure. Then, anopening is formed in a part of the protective insulation film 42 whichlies over the barrier metal layer 41. As the barrier metal layer 41, forexample, a TiN layer with a thickness of 2000 Angstroms should beformed. The protective insulation film 42 is, for example, an SiON layerwith a thickness of 3000 Angstroms.

As shown in FIG. 5B, a barrier metal layer 43 is formed on the entiresurface and a Cu film 44 is formed by electrolytic plating with thebarrier metal layer 43 as a plating electrode. Then, a barrier metallayer 45 is formed on the Cu film 44. TiW layers which have thicknessesof 2000 Angstroms and 500 Angstroms should be formed as the barriermetal layers 43 and 45, respectively. The Cu film 44 has a thickness of,for example, 3 μm.

Then, as shown in FIG. 5C, a resist pattern (not shown) with the shapeof the inductor is formed on the barrier metal layer 45 byphotolithography and the spiral inductor 40 shown in FIG. 4 is formed bywet-etching the barrier metal layer 45, the Cu film 44 and the barriermetal layer 43 with the resist pattern as a mask. In this case, theinductor 40 is connected via a contact 39 to the topmost interconnection29 formed on the topmost interconnection layer 18 underlying theinductor 40. The line width (resist width) of the inductor 40 is, forexample, 10 μm. Therefore, the inductor 40 formed has a largecross-sectional are with a cross section of substantially 10 μm wide and3 μm thick.

The same film as the Cu film which is formed, for example, at the time abonding pad to be connected to a solder ball is provided on the topmostinterconnection layer 18 of the multilayer interconnection that isconventionally formed by the damascene method may be used as the Cu film44. Accordingly, the inductor 40 of the invention can be formed at thesame time as the formation of the bonding pad, and on the same layer asthe bonding pad is, by patterning the Cu film by wet etching.

A mixture of sulfuric acid and hydrogen peroxide can be used as anetching liquid in wet etching of the Cu film. In case where the barriermetal layer is a TiW film, it can be wet-etched with the sulfuric acidand hydrogen peroxide mixture.

Next, as shown in FIG. 5D, the entire structure is covered with a coverfilm 46 of polyimide or the like, which completes the inductor for asemiconductor integrated circuit.

In the thus-constituted inductor for a semiconductor integrated circuit,the shape of the inductor is patterned by wet-etching the Cu film 44, sothat there is no substantial restrictions on the film thickness and linewidth and an inductor having a very large cross-sectional area can beformed. This can reduce the resistance of the inductor, resulting in ahigher Q value. Because the Cu film 44 is formed by wet etching in theembodiment, the sides of the interconnection of the acquired inductor 40are dented like a drum as shown in FIG. 5C. This can increase thesurface area of the inductor 40 as compared with the case where thesides of the interconnection are flat, and can thus reduce the skineffect originated from a high-frequency signal. This can also improvethe Q value of the inductor. Unlike the conventional “dishing”, thedenting of the sides of the interconnection of the inductor does notadversely affect the planarization of the film.

The second embodiment of the invention will be discussed below. In thesecond embodiment, the shape of a topmost interconnection layer 51 whichis formed on the topmost interconnection layer 18 underlying an inductor50 is formed in a spiral form like the shape of the inductor 50. Thatis, the inductor 50 and the topmost interconnection layer 51 are laidout in such a way that a circle (part notched away) which passes thecenter of the interconnection width of the inductor 50 and a circle(part notched away) which passes the center of the interconnection widthof the topmost interconnection layer 51 coincide with each other in aplan view.

Because the inductor 50 and the topmost interconnection layer 51 overlapeach other in the thus-constituted inductor for a semiconductorintegrated circuit and the topmost interconnection layer 51 serves as aninductor too, it is possible to further increase the cross-sectionalarea of the inductor. This can make the Q value of the inductor greater.

Although the inductor 40 or 50 is connected to the topmostinterconnection of the multilayer interconnection which is formed by thedamascene method in each embodiment discussed above, the invention isnot limited to this particular structure but the inductor 40 or 50 maybe connected to the topmost interconnection via a contact hole. Further,the inductor 40 or 50 may be connected to the topmost interconnection29, formed on the topmost interconnection layer 18, or the underlyinginterconnection via a contact hole by providing an interlayer insulationfilm, not the insulation film 42, between the inductor 40 or 50 and thetopmost interconnection layer 18 and forming the contact hole in thatinterlayer insulation film.

According to the invention, as described above, the inductor is providedon the (multilevel) interconnection layer formed by the damascene method(claim 1) or on the topmost interconnection layer in the (multilevel)interconnection layer (claim 6), so that the interconnection width andthe interconnection thickness do not suffer restrictions and can beincreased as needed, unlike in the conventional case where the inductoris formed on the topmost interconnection layer itself. This structurecan considerably increase the cross-sectional area of the inductor ascompared with the conventional inductor that is formed on theinterconnection layer, making it possible to reduce the resistance ofthe inductor and increase the Q value thereof.

1-17. (canceled)
 18. A semiconductor integrated circuit comprising: asubstrate; an interconnection layer formed on said substrate by adamascene method, and comprising at least one interconnection; and aconductive layer formed on said interconnection layer, said conductivelayer including a pattern thereon to form an inductor, said inductorcontacting said at least one interconnection, said conductive layercomprising: a lower protective film formed over said interconnectionlayer; a first barrier layer formed over said lower protective film; anda metal film formed over said first barrier layer.
 19. The semiconductorintegrated circuit according to claim 18, said conductive layer furthercomprising: a lower barrier layer formed under said lower protectivefilm, said lower protective film intervening between said lower barrierlayer and said first barrier layer.
 20. The semiconductor integratedcircuit according to claim 18, further comprising: an upper barrierlayer formed over said metal film.
 21. The semiconductor integratedcircuit according to claim 18, wherein said inductor comprises a spiralshape.
 22. The semiconductor integrated circuit according to claim 21,wherein said spiral shape defines a ring shaped conductor having a firstend and a second end, said first end and said second end being connectedto said at least one interconnection.
 23. The semiconductor integratedcircuit according to claim 18, wherein a side wall of said inductor isdented.
 24. The semiconductor integrated circuit according to claim 18,further comprising: a bonding pad formed outside said inductor bypatterning said conductive layer.
 25. The semiconductor integratedcircuit according to claim 18, wherein said lower barrier layercomprises a TiN layer.
 26. The semiconductor integrated circuitaccording to claim 18, wherein said lower protective film comprises aSiON layer.
 27. The semiconductor integrated circuit according to claim18, wherein said first barrier layer comprises a TiW layer.
 28. Thesemiconductor integrated circuit according to claim 18, furthercomprising: an outer protective layer formed over said inductor.
 29. Asemiconductor integrated circuit comprising: an interconnection layerformed on said substrate by a damascene method, and comprising at leastone interconnection; and a conductive layer formed on saidinterconnection layer, said conductive layer including a pattern thereonto form an inductor, said conductive layer directly contacting said atleast one interconnection.
 30. The semiconductor integrated circuitaccording to claim 29, said conductive layer comprising: a first barrierlayer formed on a top surface of said at least one interconnection; ametal film formed over said first barrier layer; and a second barrierlayer formed over said metal film.
 31. The semiconductor integratedcircuit according to claim 30, further comprising: an outer protectivelayer formed over said inductor.
 32. The semiconductor integratedcircuit according to claim 30, wherein said inductor comprises a spiralshape.
 33. The semiconductor integrated circuit according to claim 30,wherein said spiral shape defines a ring shaped conductor having a firstend and a second end, said first end and said second end being connectedto said at least one interconnection.
 34. The semiconductor integratedcircuit according to claim 30, wherein a side wall of said inductor isdented.
 35. The semiconductor integrated circuit according to claim 30,further comprising: a bonding pad formed outside said inductor bypatterning said conductive layer.